View ISL59446IRZ-T7_711076.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL59446
Data Sheet May 19, 2006 FN6261.0
500MHz Triple 4:1 Gain-of-2, Multiplexing Amplifier
The ISL59446 is a triple channel 4:1 multiplexer featuring integrated amplifiers with a fixed gain of 2, high slew-rate and excellent bandwidth for video switching. The device features a three-state output (HIZ), which allows the outputs of multiple devices to be tied together. A power-down mode (ENABLE) is included to turn off un-needed circuitry in power sensitive applications. When the ENABLE pin is pulled high, the part enters a power-down mode and consumes just 14mW.
Features
* 510MHz bandwidth into 150 * 1600V/s slew rate * High impedance buffered inputs * Internally set gain-of-2 * High speed three-state outputs (HIZ) * Power-down mode (ENABLE) * 5V operation * Supply current 11mA/ch
Ordering Information
PART NUMBER PART TAPE & (Note) MARKING REEL ISL59446IRZ IRZ 7" PACKAGE (Pb-Free) 32 Ld QFN 32 Ld QFN PKG. DWG. # L32.5x6A L32.5x6A
* Pb-free plus anneal available (RoHS compliant)
Applications
* HDTV/DTV analog inputs * Video projectors * Computer monitors * Set-top boxes * Security video * Broadcast video equipment
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59446
ISL59446IRZ-T7 IRZ
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
32 GNDA 31 IN0A 29 IN0B 27 IN0C 30 NIC 28 NIC 26 HIZ
S1 0 0
25 ENABLE 24 NIC x2 23 V+
S0 0 1 0 1 X X
ENABLE 0 0 0 0 1 0
HIZ 0 0 0 0 X 1
OUTPUT IN0 (A, B, C) IN1 (A, B, C) IN2 (A, B, C) IN3 (A, B, C) Power-Down High Z
IN1A 1 NIC 2 IN1B 3 NIC 4 IN1C 5 GNDB 6 IN2A 7 NIC 8 IN2B 9 IN2C 10 GNDC 11 IN3A 12 NIC 13 IN3B 14 NIC 15 IN3C 16 x2 THERMAL PAD x2
1 1 X X
22 OUTA 21 V20 OUTB 19 OUTC 18 S0 17 S1 S0 EN1 S1 DECODE
Functional Diagram (each channel)
EN0 IN0(A, B, C) IN1(A, B, C) EN2 EN3 IN2(A, B, C) IN3(A, B, C)
+
OUT
AMPLIFIER BIAS HIZ ENABLE
THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO VNIC = NO INTERNAL CONNECTION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59446
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . . -40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . -40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL
V+ = +5V, V- = -5V, GND = 0V, TA = 25C, VOUT = 2VP-P and RL = 500 to GND, CL = 0pF, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
+IS Enabled -IS Enabled
+IS Disabled -IS Disabled VOUT IOUT VOS Ib ROUT ROUT RIN ACL or AV LOGIC VIH VIL IIH IIL AC GENERAL PSRR Xtalk Off - ISO dG dP
Enabled Supply Current Enabled Supply Current Disabled Supply Current Disabled Supply Current Positive and Negative Output Swing Output Current Output Offset Voltage Input Bias Current HIZ Output Resistance Enabled Output Resistance Input Resistance Voltage Gain
No load, VIN = 0V, Enable Low No load, VIN = 0V, Enable Low No load, VIN = 0V, Enable High No load, VIN = 0V, Enable High VIN = 2.5V; RL = 500 VIN = 0.825V RL = 10
40 -45 3 -40 3.8 80 -40
44 -41 3.4 -6 4.0 135 -25 -2 900 0.2 10
48 -37 3.8
mA mA mA A
4.2 180 -10 -1 1150
V mA mV A M
VIN = 0V HIZ = Logic High HIZ = Logic Low VIN = 1.75V RL = 500
-4 700
1.94
1.99
2.04
V/V
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs) VH = 5V VL = 0V 200 -4
2 0.8 260 -2 320 -1
V V A A
Power Supply Rejection Ratio Channel to Channel Crosstalk Off-State Isolation Differential Gain Error Differential Phase Error
DC, PSRR V+ and V- combined VOUT = 0dBm f = 10MHz, ChX-Ch Y-Talk VIN = 1VP-P; CL = 1.1pF f = 10MHz, Ch-Ch Off Isolation VIN = 1VP-P; CL = 1.1pF NTC-7, RL = 150, CL = 1.1pF NTC-7, RL = 150, CL = 1.1pF
45
53 74 76 0.008 0.01
dB dB dB %
2
FN6261.0 May 19, 2006
ISL59446
Electrical Specifications
PARAMETER BW V+ = +5V, V- = -5V, GND = 0V, TA = 25C, VOUT = 2VP-P and RL = 500 to GND, CL = 0pF, unless otherwise specified. (Continued) DESCRIPTION Small Signal -3dB Bandwidth CONDITIONS VOUT = 0.2VP-P; RL = 500, CL = 1.1pF VOUT = 0.2VP-P; RL = 150, CL = 2.1pF Large Signal -3dB Bandwidth VOUT = 2VP-P; RL = 500, CL = 1.1pF VOUT = 2VP-P; RL = 150, CL = 1.1pF FBW 0.1dB Bandwidth VOUT = 2VP-P; RL = 500, CL = 1.1pF VOUT = 2VP-P; RL = 150, CL = 1.1pF SR Slew Rate 25% to 75%, RL = 150, Input Enabled, CL = 2.1pF MIN TYP 620 530 280 260 160 50 1600 MAX UNIT MHz MHz MHz MHz MHz MHz V/s
TRANSIENT RESPONSE tr, tf Large Signal tr, tf, Small Signal
ts 0.1%
Large Signal Rise, Fall Times, tr, tf, 10% - 90% Small Signal Rise, Fall Times, tr, tf, 10% - 90% Settling TIme to 0.1%
VOUT = 2VP-P; RL = 500, CL = 1.1pF VOUT = 2VP-P; RL = 150, CL = 2.1pF VOUT = 0.2VP-P; RL = 500, CL = 1.1pF VOUT = 0.2VP-P; RL = 150, CL = 2.1pF VOUT = 2VP-P; RL = 500, CL = 1.1pF VOUT = 2VP-P; RL = 150, CL = 2.1pF
1.2 1.3 0.7 0.9 7.2 8.2 4 4.3
ns ns ns ns ns ns ns ns
ts 1%
Settling TIme to 1%
VOUT = 2VP-P; RL = 500, CL = 1.1pF VOUT = 2VP-P; RL = 150, CL = 2.1pF
SWITCHING CHARACTERISTICS VGLITCH Channel -to-Channel Switching Glitch VIN = 0V, RL = 500; CL = 1.1pF VIN = 0V, RL = 150; CL = 2.1pF Enable Switching Glitch VIN = 0V, RL = 500; CL = 1.1pF VIN = 0V, RL = 150; CL = 2.1pF HIZ Switching Glitch VIN = 0V, RL = 500; CL = 1.1pF VIN = 0V, RL = 150; CL = 2.1pF tSW-L-H tSW-H-L tpd Channel Switching Time Low to High Channel Switching Time High to Low Propagation Delay 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% to 10% 90 15 1.8 1.35 340 340 24 24 0.55 mVP-P mVP-P VP-P VP-P mVP-P mVP-P ns ns ns
3
FN6261.0 May 19, 2006
ISL59446 Typical Performance Curves
10 8 NORMALIZED GAIN (dB) 6 4 2 0 -2 -4 -6 -8 -10 1M CL INCLUDES 0.6pF BOARD CAPACITANCE 10M CL = 3.3pF CL = 2.1pF CL = 1.1pF CL = 0.6pF 100M 1G VOUT = 0.2VP-P CL = 8.8pF NORMALIZED GAIN (dB) CL = 7.4pF CL = 6.2pF CL = 4.5pF
VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
10 8 6 4 2 0 -2 -4 -6 -8 -10 1M CL INCLUDES 0.6pF BOARD CAPACITANCE 10M CL = 4.5pF CL = 3.3pF CL = 2.1pF CL = 0.6pF 100M 1G VOUT = 0.2VP-P CL = 12.6pF CL = 10.6pF CL = 8.8pF CL = 6.2pF
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 1M CL INCLUDES 0.6pF BOARD CAPACITANCE 10M 100M 1G CL = 2.1pF CL = 0.6pF CL = 5.3pF VOUT = 2VP-P CL = 8.8pF
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD
10 8 NORMALIZED GAIN (dB) 6 4 2 0 -2 -4 -6 -8 -10 1M CL INCLUDES 0.6pF BOARD CAPACITANCE 10M 100M FREQUENCY (Hz) 1G CL = 2.1pF CL = 0.6pF CL = 5.3pF VOUT = 2VP-P CL = 12.6pF
FREQUENCY (Hz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD
2 1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 1M 10M VOUT = 0.2VP-P CL = 1.1pF
RL = 1k RL = 500 NORMALIZED GAIN (dB)
0.3 VOUT = 0.2VP-P 0.2 0.1 RL = 150 CL = 2.1pF
RL = 250 RL = 150
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 RL = 500 CL = 1.1pF
100M
1G
-0.7 1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs RL
FIGURE 6. 0.1dB GAIN FLATNESS
4
FN6261.0 May 19, 2006
ISL59446 Typical Performance Curves
100 VSOURCE = 2VP-P OUTPUT IMPEDANCE () OUTPUT IMPEDANCE ()
VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified. (Continued)
10k VSOURCE = 2VP-P
10
1k
1
100
0.1 0.1M
1M
10M FREQUENCY (Hz)
100M
1G
10 0.1M
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 7. ZOUT vs FREQUENCY - ENABLED
FIGURE 8. ZOUT vs FREQUENCY - HIZ
1M VSOURCE = 2VP-P 100k INPUT IMPEDANCE ()
10 VSOURCE = 0.5VP-P 0 PSRR (V-) -10
10k PSRR (dB) -20 -30 -40 PSRR (V-) 10 -50 -60 0.3M
1k
100
1 0.3M
1M
10M 100M FREQUENCY (Hz)
1G
1M
10M 100M FREQUENCY (Hz)
1G
FIGURE 9. ZIN vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
0 -10 -20 VIN = 1VP-P VOLTAGE NOISE (nV/Hz) 100M 1G 60 50 40 30 20 10 0 100
CROSSTALK RL = 500 -30 INPUT X TO OUTPUT Y RL = 150 OFF ISOLATION RL = 500 -50 INPUT X TO OUTPUT X RL = 150
-40 (dB)
-60 -70 -80 -90 -100 0.1M 1M 10M FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
FIGURE 11. CROSSTALK AND OFF ISOLATION
FIGURE 12. INPUT NOISE vs FREQUENCY
5
FN6261.0 May 19, 2006
ISL59446 Typical Performance Curves
NORMALIZED PHASE () NORMALIZED GAIN (dB) 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.01 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -4 -3 -2 -1 1 0 VOUT DC (V) 2 3 4
VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified. (Continued)
NORMALIZED PHASE () NORMALIZED GAIN (dB) 0.01 0.008 0.006 0.004 0.002 0 -0.002 -0.004 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -4 -3 -2 -1 0 1 2 3 4
VOUT DC (V)
FIGURE 13. DIFFERENTIAL GAIN AND PHASE; VOUT = 0.2VP-P, FO = 3.58MHz, RL = 500
FIGURE 14. DIFFERENTIAL GAIN AND PHASE; VOUT = 0.2VP-P, FO = 3.58MHz, RL = 150
VOUT = 0.2VP-P 0.2 OUTPUT VOLTAGE (V) RL = 500 CL = 1.1pF OUTPUT VOLTAGE (V) 0.2
VOUT = 0.2VP-P RL = 150 CL = 2.1pF
0.1
0.1
0
0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE; RL = 500
FIGURE 16. SMALL SIGNAL TRANSIENT RESPONSE; RL = 150
VOUT = 2VP-P 2.0 OUTPUT VOLTAGE (V) RL = 500 CL = 1.1pF OUTPUT VOLTAGE (V) 2.0
VOUT = 2VP-P RL = 150 CL = 2.1pF
1.0
1.0
0
0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 17. LARGE SIGNAL TRANSIENT RESPONSE; RL = 500
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE; RL = 150
6
FN6261.0 May 19, 2006
ISL59446 Typical Performance Curves
50 INPUT RISE, FALL TIMES VOUT = 2VP-P <175ps VOUT = 1.4VP-P
VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified. (Continued)
50 INPUT RISE, FALL TIMES <175ps VOUT = 2VP-P VOUT = 1.4VP-P
40 OVERSHOOT (%)
40 OVERSHOOT (%)
30
30
20 VOUT = 1VP-P 10 VOUT = 0.2VP-P
20 VOUT = 1VP-P 10 VOUT = 0.2VP-P
0 2 4 CL (pF) 6 8 10
0
2
4
CL (pF)
6
8
10
FIGURE 19. PULSE OVERSHOOT vs VOUT, CL; RL = 500
FIGURE 20. PULSE OVERSHOOT vs VOUT, CL; RL = 150
S0, S1 50 TERM. 1V/DIV
VIN = 0V
1V/DIV
S0, S1 50 TERM.
VIN = 1V
0 20mV/DIV VOUT A, B, C 1V/DIV 0 20ns/DIV
0
0
VOUT A, B, C 20ns/DIV
FIGURE 21. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
FIGURE 22. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V
ENABLE 50 TERM. 1V/DIV
VIN = 0V
ENABLE 50 TERM. 1V/DIV
VIN = 1V
0
0
1V/DIV
2V/DIV 40ns/DIV
VOUT A, B, C 0
0
VOUT A, B, C 40ns/DIV
FIGURE 23. ENABLE SWITCHING GLITCH VIN = 0V
FIGURE 24. ENABLE TRANSIENT RESPONSE VIN = 1V
7
FN6261.0 May 19, 2006
ISL59446 Typical Performance Curves
HIZ 50 TERM. 1V/DIV 1V/DIV
VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified. (Continued)
VIN = 0V
HIZ 50 TERM.
VIN = 1V
0 200mv/DIV
0
0 VOUT A, B, C 20ns/DIV
2V/DIV
VOUT A, B, C 0 20ns/DIV
FIGURE 25. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 26. HIZ TRANSIENT RESPONSE VIN = 1V
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 2.857W POWER DISSIPATION (W) QFN32 JA = 35C/W POWER DISSIPATION (W) 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 1 0.8 1.2
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
758mW 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QFN32 JA = 125C/W
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
8
FN6261.0 May 19, 2006
ISL59446 Pin Descriptions
ISL59446 (32 LD QFN) 1 2, 4, 8, 13, 15, 24, 28, 30 3 5 6 7 9 10 11 12 14 16 17 18 19 20 21 22 23 25 PIN NAME IN1A NIC IN1B IN1C GNDB IN2A IN2B IN2C GNDC IN3A IN3B IN3C S1 S0 OUTC OUTB VOUTA V+ ENABLE Circuit 1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 3 Circuit 3 Circuit 4 Circuit 3 Circuit 4 Circuit 2 EQUIVALENT CIRCUIT Circuit 1 DESCRIPTION Channel 1 input for output amplifier "A" Not Internally Connected; it is recommended these pins be tied to ground to minimize crosstalk. Channel 1 input for output amplifier "B" Channel 1 input for output amplifier "C" Ground pin for output amplifier "B" Channel 2 input for output amplifier "A" Channel 2 input for output amplifier "B" Channel 2 input for output amplifier "C" Ground pin for output amplifier "C" Channel 3 input for output amplifier "A" Channel 3 input for output amplifier "B" Channel 3 input for output amplifier "C" Channel selection pin MSB (binary logic code) Channel selection pin. LSB (binary logic code) Output of amplifier "C" Output of amplifier "B" Negative power supply Output of amplifier "A" Positive power supply Device enable (active low). Internal pull-down resistor ensures device is active with no connection to this pin. A logic High puts device into power-down mode and only the logic circuitry is active. Logic states are preserved post power-down. Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. Channel 0 for output amplifier "C" Channel 0 for output amplifier "B" Channel 0 for output amplifier "A" Ground pin for output amplifier "A"
V+ LOGIC PIN 21k 33k VVCIRCUIT 2 CIRCUIT 3 + 1.2V GND V+ OUT V-
26
HIZ
Circuit 2
27 29 31 32
IN0C IN0B IN0A GNDA
Circuit 1 Circuit 1 Circuit 1 Circuit 4
V+
IN
CIRCUIT 1
V+ GNDA GNDB GNDC VCIRCUIT 4 CAPACITIVELY COUPLED ESD CLAMP
THERMAL HEAT SINK PAD ~1M VSUBSTRATE
9
FN6261.0 May 19, 2006
ISL59446 AC Test Circuits
ISL59446 VIN 50 or 75 x2 *CL 1.1pF RL 500, or 150 LCRIT VOUT
Application Information
General
Key features of the ISL59446 include a fixed gain of 2, buffered high impedance analog inputs and excellent AC performance at output loads down to 150 for video cabledriving. The current feedback output amplifiers are stable operating into capacitive loads. For the best isolation and crosstalk rejection, all GND pins and NIC pins must connect to the GND plane.
*CL Includes PCB trace capacitance FIGURE 29A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59446 VIN 50 or 75 x2
AC Design Considerations
LCRIT RS
CL
CS
RL 500, or 75
FIGURE 29B. INTER-STAGE APPLICATION CIRCUIT
ISL59446 VIN 50 x2
LCRIT
RS 56.2
TEST EQUIPMENT 50
475 *CL 1.1pF
*CL Includes PCB trace capacitance FIGURE 29C. 500 TEST CIRCUIT WITH 50 LOAD
ISL59446 VIN 50,or 75 x2
LCRIT
RS 86.6
TEST EQUIPMENT 50
High speed current-feed amplifiers are sensitive to capacitance at the inverting input and output terminals. The ISL59446 has an internally set gain of 2, so the inverting input is not accessible. Capacitance at the output terminal increases gain peaking (Figure 1) and pulse overshoot (Figures19, 20). The AC response of the ISL59446 is optimized for a total output capacitance of up to 2.1pF over the load range of 150 to 500. When PCB trace capacitance and component capacitance exceed 2pF, pulse overshoot becomes strongly dependent on the input pulse amplitude and slew rate. This effect is shown in Figures 19 and 20, which show approximate pulse overshoot as a function of input slew rate and output capacitance. Fast pulse rise and fall times (<150ns) at input amplitudes above 0.2V, cause the input pulse slew rate to exceed the 1600V/s output slew rate of the ISL59446. At 125ps rise time, pulse input amplitudes >0.2V cause slew rate limit operation. Increasing levels of output capacitance reduce stability resulting in increased overshoot, and settling time. PC board trace length should be kept to a minimum in order to minimize output capacitance and prevent the need for controlled impedance lines. At 500MHz trace lengths approaching 1" begin exhibiting transmission line behavior and may cause excessive ringing if controlled impedance traces are not used. Figure 29A shows the optimum inter-stage circuit when the total output trace length is less than the critical length of the highest signal frequency. For applications where pulse response is critical and where inter-stage distances exceed LCRIT, the circuit shown in Figure 29B is recommended. Resistor RS constrains the capacitance seen by the amplifier output to the trace capacitance from the output pin to the resistor. Therefore, RS should be placed as close to the ISL59446 output pin as possible. For inter-stage distances much greater than LCRIT, the back-loaded circuit shown in Figure 29E should be used with controlled impedance PCB lines, with RS and RL equal to the controlled impedance. For applications where inter-stage distances are long, but pulse response is not critical, capacitor CS can be added to low values of RS to form a low-pass filter to dampen pulse overshoot. This approach avoids the need for the large gain correction required by the -6dB attenuation of the
118 *CL 2.1pF
*CL Includes PCB trace capacitance FIGURE 29D. 150 TEST CIRCUIT WITH 50 LOAD
ISL59446 VIN 50 or 75 x2
LCRIT
RS
TEST EQUIPMENT 50 or 75
50 or 75 *CL 2.1pF
*CL Includes PCB trace capacitance FIGURE 29E. BACKLOADED TEST CIRCUIT FOR 75 VIDEO CABLE APPLICATION
AC Test Circuits
Figures 29C and 29D illustrate the optimum output load for testing AC performance at 500 and 150 loads. Figure 29E illustrates the optimum output load for 50 and 75 cable-driving.
10
FN6261.0 May 19, 2006
ISL59446
back-loaded controlled impedance interconnect. Load resistor RL is still required but can be 500 or greater, resulting in a much smaller attenuation factor.
HIZ State
An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 20ns (Figure 26) by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output impedance is ~1000 (Figure 8). The supply current during this state is same as the active state.
Control Signals
S0, S1, ENABLE, HIZ - These are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three amplifiers are switched simultaneously from their respective inputs. The ENABLE pin is used to disable the part to save power, and the HIZ pin to set the output stage in a high impedance state. For control signal rise and fall times less than 10ns the use of termination resistors close to the part may be necessary to prevent reflections and to minimize transients coupled to the output.
ENABLE and Power-Down States
The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The power-down state is established within approximately 200ns (Figure 24), if a logic high (>2V) is placed on the ENABLE pin. In the power-down state, the output has no leakage but has a large variable capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited power-down output impedance.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins to the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 30) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip line are used.
V+ SUPPLY SCHOTTKY PROTECTION LOGIC POWER GND SIGNAL DECOUPLING CAPS V- SUPPLY S0 GND IN0 IN1 VVVV+ VVV+ V+ OUT V+ V+ LOGIC CONTROL EXTERNAL CIRCUITS
FIGURE 30. SCHOTTKY PROTECTION CIRCUIT
11
FN6261.0 May 19, 2006
ISL59446
* Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC decoupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible - avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V- supply through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND as this could result in large back biased currents flowing between GND and V-. The ISL59446 the package with pad dimensions of D2 = 2.48mm and E2 = 3.4mm. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. * The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible a 1" x 1" pad area is sufficient for the ISL59446 that is dissipating 0.5W in +50C ambient. Pad area requirements should be evaluated on a case by case basis.
12
FN6261.0 May 19, 2006
ISL59446 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
A D N (N-1) (N-2) B
L32.5x6A (One of 10 Packages in MDP0046) 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220)
MILLIMETERS SYMBOL A A1 MIN 0.80 0.00 NOMINAL 0.90 0.02 5.00 BSC 2.48 REF 6.00 BSC 3.40 REF 0.45 0.20 0.50 0.22 0.20 REF 0.50 BSC 32 REF 7 REF 9 REF 0.55 0.24 MAX 1.00 0.05 NOTES 4 6 5 Rev 0 9/05 NOTES:
1 2 3
D
PIN #1 I.D. MARK E
D2 E E2 L b
2X 0.075 C
c
2X 0.075 C
(N/2) TOP VIEW N LEADS 0.10 M C A B (N-2) (N-1) N b
e N ND NE
L
PIN #1 I.D. 3 1 2 3
1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the "E" side of the package (or Y-direction).
(E2)
NE 5 (N/2)
6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown.
(D2) BOTTOM VIEW
7
e C
0.10 C (c) 2
SEATING PLANE 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X"
C
A
(L) A1 N LEADS
SIDE VIEW
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6261.0 May 19, 2006

▲Up To Search▲

Price & Availability of ISL59446IRZ-T7

	To Download ISL59446IRZ-T7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .